So-called surface technologies (as contrasted with bulk technologies) enable the size of electromechanical structures that are made on silicon to be reduced. These technologies rely on using a stack of at least three layers: a mechanical layer (thickness typically 0.1 micrometer (μm) to 100 μm); a sacrificial layer (thickness typically 0.1 μm to 5 μm); and a support (thickness typically 10 μm to 1000 μm). Selective chemical etching of the sacrificial layer makes it possible to form active structures in the mechanical layer that are locally independent of the support. The non-etched zones of the sacrificial layer serve to make so-called “anchor” zones whereby the mechanical structure is connected to the support.
Any particular given method is characterized by selecting a pair of materials for constituting the mechanical layer and the sacrificial layer, and by selecting the method used for associating them with the support. The choice of method depends on criteria that differ depending on the type of component made, but in order to have a method that is flexible and suitable for adapting to a wide range of requirements, the main technological criteria retained are as follows:                the quality of the mechanical layer, firstly the stability of its mechanical properties, but also the precision with which its dimensions can be controlled, and in particular its thickness;        the possibility of controlling the lateral dimensions of anchor zones by inserting, in the sacrificial layer, zones that are not attacked by the chemical etching so as to avoid being dependent on controlling etching by duration, where such control is sensitive to the shape of the structure;        the possibility of having one or more levels of electrical interconnection above and/or below the mechanical layer, suitable for acting as electrodes, where necessary;        compatibility with adding a silicon cap, in particular for inertial structures; and        the possibility of having distinct thicknesses of silicon in a single component.        
The family of methods in the most widespread use rely on the silicon (mechanical layer) and silica (sacrificial layer) materials pair associated with selective etching of the silica with HF (in the liquid or the vapor phase). This family forms part of silicon-on-insulator (SOI) MEMS technology.
The simplest SOI-MEMS methods make use of two layers of SiO2 and Si made by successive deposits of material, e.g. by plasma-enhanced chemical vapor deposition (PECVD) or by low pressure chemical vapor deposition (LPCVD) on a silicon support (solid silicon substrate). These methods are advantageous, because:                the thickness of the mechanical layer is controlled by the length of time the silicon layer is deposited;        the anchor zones are very well controlled since it is possible to use the mechanical layer directly by locally etching the oxide layer prior to depositing the silicon; and        it is possible to make interconnections at different levels.        
Nevertheless, the silicon constituting the mechanical layer deposited on the oxide is polycrystalline silicon, which makes it more difficult to control its mechanical qualities (controlling level of stresses, stability, . . . ), and puts a limit on the thickness that can be obtained.
Known improvements to those methods make it possible to use monocrystalline silicon as the mechanical layer, thus obtaining mechanical properties that are considered as being better, and also obtaining a range of accessible thicknesses that is greater.
Three major families of known methods of making MEMS out of monocrystalline silicon using SOI-MEMS technology may be mentioned, which families differ by the method used for making the substrate that includes the complete stack:
1) The starting substrate is an SOI substrate having a fine layer of Si of the microelectronic type and of controlled thickness (typically of the order of 100 nanometers (nm)), e.g. made using the so-called “Smart Cut” (registered trademark) cleaving technique. The SiO2 layer provides insulation relative to the substrate and it is used as a sacrificial layer, with the fine silicon layer serving as a basis for epitaxial growth of silicon, thereby enabling a mechanical layer to be obtained that is made of monocrystalline material.
It is also known to make interconnection levels over a mechanical layer and anchors out of SiN or polycrystalline Si as described in the article “Polysilicon packaging and a new anchoring technology for thick SOI-MEMS—dynamic response model and application to over-damped inertial sensors” by B. Diem et al. (13th International Conference on Solid State Sensors, Actuators, and Microsensors, Seoul, Jun. 5-9, 2005, pp. 527-530).
2) The initial substrate is a silicon substrate having an oxide layer. The mechanical layer is made by bonding a second substrate of thick silicon which is subsequently thinned by rectification and polishing (cf. PCT application WO 2006/035031). In that method, the sacrificial layer is used as a bonding layer and the quality of bonding is critical since it must guarantee that the chemical etching is uniform. Implementing anchor zones in the sacrificial layer prior to bonding is possible, but that requires substrate bonding to be performed with heterogeneous surfaces.
3) The initial substrate is a thick silicon substrate on which there are deposited the sacrificial oxide layer and then a functionalization multilayer of SiN associated with polycrystalline Si, and finally a final bonding layer of polycrystalline Si. This initial stack is bonded onto a second silicon substrate that acts as a support. Thereafter, the thick base substrate is thinned by rectification and polishing to provide a mechanical layer that is used for the electromechanical system (cf. the article “Capacitive accelerometer with high aspect ratio single crystalline silicon microstructure using the SOI structure with polysilicon-based interconnect technique”, by T. Yamamoto et al., published in MEMS 2000, the 13th International Annual Conference, Jan. 23-27 2000, Miyazaki, Japan, pp. 514-519). The proposed method makes it possible to provide anchor zones of polycrystalline Si, interconnection layers, and buried electrodes, and the bonding layer is distinct from the sacrificial layer, which means that the quality of bonding is less critical, since it then has mechanical functions only.
With inertial structures, it is necessary to provide a cap over the active structure both for the purpose of protecting it and also for ensuring that the atmosphere in which the structure is located is controlled in terms of pressure and composition. The cap must not give rise directly or indirectly to stresses on the component (in particular when the base substrate is thinned so as to reduce the total thickness of the device).
A first solution is to place a cutout MEMS structure in a package. That non-collective technology significantly increases the cost of the component and also increases its total volume.
Known technologies for providing protection over MEMS structures in collective manner are of two types:                either sealing a wafer of silicon having cavities over the MEMS structures. By way of example this is proposed in the method of sealing with glass frit and a contact pass under the structure (as described for example in U.S. Pat. No. 6,391,673);        or making a cap as a thin layer. For example, in above method 1), it is possible to make a cap out of polycrystalline Si on top of the MEMS structure, e.g. as described in the above-mentioned article by B. Diem.        
Solutions that require a wafer of silicon to be fitted make use of a third substrate. Sealing technology requires a bonding area that is sufficient to provide mechanical strength, thereby increasing the total area of the component.
Solutions exist involving fitting a silicon cap while providing an electrical connection (reference: AuSn on a component: Q. Wang et al., Application of Au—Sn eutectic bonding in hermetic radio-frequency microelectromechanical system wafer level packaging, Journal of Electronic Materials, Vol. 35, No. 3, 2006). For the time being, those technologies are usable industrially only at component scale, and in addition the connection is made with the help of a metal alloy that is complex to provide.
The solution associated with above method 1) relies on using a deposit of polycrystalline Si, and it enables contacts to be transferred via the cap. However the nature of the deposit used requires stress to be monitored, which is difficult to do industrially. Such monitoring is particularly required when the support is thinned so as to reduce the total thickness of the component. In addition, the thickness of the cap is limited to about ten micrometers, making it difficult to use the face of the cap for three-dimensional integration technologies.
In methods of the SOI type that use a monocrystalline active layer, it is not presently possible to structure the mechanical layer in the third dimension.
The main known solutions for making MEMS on silicon rely on using a sacrificial layer of oxide. The advantage of this choice is the excellent selectivity of etching oxide and stopping on silicon, which is the material used most widely as the mechanical layer. However it is not possible to grow a monocrystalline material epitaxially on such a layer, thereby making it necessary to find alternative methods for making the assembly comprising the support, the sacrificial layer, and the mechanical layer when it is desired to obtain a mechanical layer that is made of monocrystalline material. The oxide sacrificial layer is not a good candidate for structuring the mechanical layer by including a sacrificial layer therein.
A known solution for making a sacrificial layer compatible with growing silicon epitaxially consists in using SiGe as the sacrificial layer, since it is possible to grow SiGe epitaxially on silicon and to grow silicon epitaxially on SiGe. The limitation of that solution is the thickness of SiGe that can be obtained without giving rise to high levels of stress in the subsequently deposited layer of monocrystalline silicon. In addition, the selectivity of etching SiGe and stopping on Si is only medium. Another known solution consists in using porous Si. Porous Si can be made on the surface of a silicon substrate without any constraint of limiting thickness, and it is subsequently possible to grow a new layer of Si epitaxially (see article by P. Steiner, A. Richter, and W. Lang, “Using porous silicon as a sacrificial layer”, J. Micromech. Microeng. 3 (1993) 3236). The limit on that solution is the relatively poor selectivity of etching porous Si and stopping on Si.